Sorin D. COTOFANA
Professor, Department of Software and Computer Technology, Delft University of Technology, The Netherlands
Research interests:
design and implementation of dependable/reliable systems out of unpredictable/unreliable components, ageing assessment/prediction and lifetime reliability aware resource management, unconventional computation paradigms and computation with emerging nano-devices
Keynote address:
Are Unpaved Roads to Rome Better Than the Paved Ones?
Abstract:
For many decades we are witnessing an on-going increase in Integrated Circuit performance mainly due to advances in fabrication technology and improvements in computational paradigms. IC feature size reduction has been an important contributing factor to the dramatic increase in the processing power of arithmetic circuits. However, it is generally accepted that, sooner or later, MOSFET-based circuits cannot be reduced further in (feature) size due to fundamental physical restrictions. Therefore, several emerging nano-technologies are currently being investigated, e.g., Single Electron Tunnelling (SET) junctions, Nano Electro Mechanical FETs, memristive devices, etc.
Currently, there is a wide gap between the research on nano-scale devices and the research on their utilisation in computer technology. Most of the community is attempting to mould emerging nanodevices to fit into the CMOS centric design methodology, i.e., is seeking a FET replacement nanodevice. However, essentially speaking, these new nanodevices exhibit behaviours that are substantially different than that of the well-established MOS devices and if we are to fully utilise the potential of these emerging devices we should adapt the paradigms to their specifics. Moreover, inherent to very small devices are parameter variations and low reliability, which also fundamentally impact the way we design/program computer systems. Together with some other sources of variance, e.g., temperature and power supply variations, these parameter variation cause significant fluctuations in the time required by a part of a circuit to perform its computational task, which has to be dealt with at the circuit and architecture levels.
In this presentation we first discuss nano-era specific challenges and opportunities one has to face and/or make use of, when designing and programming computation platforms. We than argue that traditional approaches, which are effective for CMOS, may not be that effective for emerging nanodevices. To make our case we address the following questions:
First we introduce 3 SET based logic families: Single Electron Encoded Logic, which builds upon Threshold Logic, and Electron Counting, and Brownian computing, which follow completely unorthodox paradigms. Subsequently, we present ultra low power NEMFET based short circuit current free logic and its utilisation in power management and memory design. Finally, we briefly describe an Averaging Cell based fault tolerant structure, which relies on noise to take advantage of the Dynamic Stochastic Resonance phenomenon to increase its performance.
Based on the discussed approaches we conclude that if we are willing to leave behind the traditional way of computation and embrace new paradigms, we can solve nano-era specific challenge and make a better use of emerging devices.
Currently, there is a wide gap between the research on nano-scale devices and the research on their utilisation in computer technology. Most of the community is attempting to mould emerging nanodevices to fit into the CMOS centric design methodology, i.e., is seeking a FET replacement nanodevice. However, essentially speaking, these new nanodevices exhibit behaviours that are substantially different than that of the well-established MOS devices and if we are to fully utilise the potential of these emerging devices we should adapt the paradigms to their specifics. Moreover, inherent to very small devices are parameter variations and low reliability, which also fundamentally impact the way we design/program computer systems. Together with some other sources of variance, e.g., temperature and power supply variations, these parameter variation cause significant fluctuations in the time required by a part of a circuit to perform its computational task, which has to be dealt with at the circuit and architecture levels.
In this presentation we first discuss nano-era specific challenges and opportunities one has to face and/or make use of, when designing and programming computation platforms. We than argue that traditional approaches, which are effective for CMOS, may not be that effective for emerging nanodevices. To make our case we address the following questions:
- Should Boolean algebra always be the foundation on which digital hardware is built?
- Are nano-mechanical devices capable to contribute to energy consumption reduction?
- Can noise and ageing be embraced instead of suppress and utilised in computation and reliability improvement?
- Are nano-mechanical devices capable to contribute to energy consumption reduction?
- Can noise and ageing be embraced instead of suppress and utilised in computation and reliability improvement?
First we introduce 3 SET based logic families: Single Electron Encoded Logic, which builds upon Threshold Logic, and Electron Counting, and Brownian computing, which follow completely unorthodox paradigms. Subsequently, we present ultra low power NEMFET based short circuit current free logic and its utilisation in power management and memory design. Finally, we briefly describe an Averaging Cell based fault tolerant structure, which relies on noise to take advantage of the Dynamic Stochastic Resonance phenomenon to increase its performance.
Based on the discussed approaches we conclude that if we are willing to leave behind the traditional way of computation and embrace new paradigms, we can solve nano-era specific challenge and make a better use of emerging devices.
Sorin D. COTOFANA received the M.Sc. degree in Computer Science from the Politehnica University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He is currently an Associate Professor with the Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, the Netherlands. His current research is focussed on: (i) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components; (ii) ageing assessment/prediction and lifetime reliability aware resource management; and (iii) unconventional computation paradigms and computation with emerging nano-devices. He (co-)authored 37 journal, 176 international conference, and 38 local conferences and workshops papers. He received 12 international conferences best paper awards, e.g., 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, 2001 International Conference on Computer Design; He is currently Associate Editor for IEEE Transactions on Nanothechnology and Nano Communication Networks journals and has been actively involved in the organization of many international conferences. He is a HiPEAC member, a senior IEEE member (Circuits and System Society (CASS) and Computer Society), Chair of the GIga-Nano IEEE CASS Technical Committee, and IEEE Nano Council CASS representative.
